| Conference: | DVCLUB Europe | Formal Verification Adoption Made Easy |
| Speaker: | Vlada Kalinic, Product Specialist (for SystemC), OneSpin A Siemens Business |
| Abstract: | The use of high-level synthesis (HLS) has substantial benefits in terms of flexibility and time-to-market. HLS transforms algorithmic and potentially untimed design models, often written in SystemC and C++, to fully timed RTL design blocks. But as you raise the abstraction level of your design, it becomes more natural to also raise the level of the verification. At the pre-HLS algorithmic level, verifying the design directly against its specification with less concern for coding detail is a requirement. However, the verification options for SystemC and C++ designs have not kept pace with the synthesis technology. Due to the limited availability of SystemC tools, much of the verification task is performed on the resulting synthesized RTL code, introducing a level of indirection that makes correcting issues at the SystemC/C++ level complex and time consuming. Specific issues related to this abstract design level may be easily tackled with the right formal verification environment. We’ll show you how automated formal technologies can be used to ease the debug and functional verification burden of SystemC/C++ code prior to high-level synthesis.
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| Speaker Biography: | Vlada Kalinic is the Product Specialist of SystemC in OneSpin, A Siemens Business, and is involved in the evaluations with the new customers as well supporting the current portfolio of the customers to improve the SystemC/C++ verification flows. Vlada holds a master’s degree with honors in Electrical and Computer Engineering, Embedded Systems and Algorithms from the University of Novi Sad (Serbia). Prior to Mentor/Siemens, Vlada worked with OneSpin for 5+ years and was involved in various successful evaluations with SystemC customers. |
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