Tessolve participated at the SemiconIndia 2022, the post-COVID gigantic conference in the Semiconductor industry. The Hon’ble Prime Minister of India, Shri Narendra Modi, inaugurated the conference via Video Conference on...
Tessolve, a Hero Electronix venture and an end-to-end engineering solution partner for semiconductor and system companies, is pleased to announce the appointment of two industry veterans, Huzefa Cutlerywala as Senior...
Tessolve announces its inaugural run of its Test Engineering Lab in San Jose on Mar 23. We offer access to test engineering and program development experts and access to testers....
We are glad to announce the release of the Jan 22 edition of our Newsletter, First Bin. The newsletter contains a note from our CEO’s Desk, Tessolve Showcase article, and...
Tessolve’s and DynamoEdge have announced a partnership to deliver the fastest end-to-end mobility solutions powered by AT&T 5G. The strategic collaboration of Tessolve with DynamoEdge has paved the way to...
The partnership will allow showcasing our end-to-end capabilities in supporting Industrial and Automotive OEM’s safety-related Hardware modules, associated Software technology, innovative Automotive product development, and system validation for various customers...
Tessolve has joined the GlobalFoundries® (GF®) Design Enablement Network Program. The strategic partnership with GF aims to bring state-of-the-art design solutions across multiple end markets including automotive, industrial, server, graphics,...
We are thrilled to share another milestone to Tessolve’s journey with the recognition Tessolve has achieved by SiliconIndia among The 10 Best Electronics Companies to Work For in Bangalore 2021....
Tessolve is now a member of the Arm® Approved Design Partner program, a global network of product design service companies endorsed by Arm. Tessolve's strategic partnership with ARM aims at...
Tessolve, a Hero Electronix venture expands its operations to multiple locations globally this year, including Japan, Taiwan, Thailand, Philippines, and Vietnam to accelerate Tessolve’s ability to provide value to customers...
The verification of processor architectures designed for Machine Learning (ML) applications represent a departure from conventional techniques. Conventional constrained random testbenches, which focus on stimulus driving coverage, cannot scale for many ML algorithm realizations. ML architectures involve neural networks of processors that “learn” by manipulating coefficients across the network to match ideal outputs to a large quantity of input data. Furthermore, smart compiler technology is employed to leverage the many paths available in the network. An effective verification strategy can leverage planning algorithms that start with the desired output and optimize input values to achieve that output. Ensuring the paths that the compiler might trigger have all been tested, and that the test content can scale from individual processors to the entire network are critical challenges. Breker will share various approaches to this problem, developed through cooperation with three noted AI processor providers.
3 Key Points:
Current verification methodologies cannot scale to meet ML processor challenges
ML verification approach: consider desired outputs, optimize inputs to match
Test Suite Synthesis enable planning algorithm approach to target ML requirements
An Emulation Strategy for Artificial Intelligence Designs
The emergence of Artificial Intelligence is the “next big thing” and presents a unique opportunity for disruptive semiconductor development. End applications could range from ADAS, to 3D facial recognition, to voice and image processing, or to intelligent search. The SoCs for AI applications whether targeted for training or inference will have their own unique characteristics, but present quite common verification challenges that we will present in this session.
Supporting designs as big as 15 billion gates, Mentor’s Veloce Strato has unique virtualization capabilities that enable highly accurate pre-silicon execution of AI benchmarking applications like MLPerf. The Veloce Power App enables analysis of peak and average. We will cover how Veloce Strato and its supporting solutions are the best tool to help address the verification challenges of SoCs targeted for AI applications.
Most AI chips and hardware accelerators that power machine learning (ML) and deep learning (DL) applications include floating-point units (FPUs). Algorithms used in neural networks are often based on operations that use multiplication and addition of floating-point values. FPUs are difficult to implement. The IEEE 754 standard defines many corner-case scenarios and non-ordinary values. Even a minor rounding mistake could accumulate over many iterations and produce a large error. An FPU formal verification app compliant with IEEE-754 provides an efficient and rigorous solutions to FPU functional verification
3 Key Points:
Floating-point unit (FPU) for AI chips
FPU Formal Verification App
Compliance with IEEE-754
Name: Mike Bartley
Designation: Senior Vice President – VLSI Design
Title: Introduction
Biography:
Mike Bartley has a PhD in Mathematics from Bristol University, an MSc in Software Engineering, an MBA from the Open University and over 25 years of experience in software testing and hardware verification. He has built and managed state-of-the-art test and verification teams in a number of companies who still use the methodologies he established. Since founding TVS in 2008 he has grown the company to over 100 employees worldwide. Dr Bartley is Chair of both the Bristol branch of the British Computer Society and the West of England Bristol Local Enterprise Partnership (LEP). He has had over 50 articles and presentations published on the subjects of hardware verification, software testing and outsourcing.